Modern digital computers, particularly personal computers, currently are designed to accommodate memory chips of different sizes, and of different numbers. The memory chips are inserted on circuit boards in physical locations known as memory banks. The memory chips currently used are dynamic random access memory (DRAM) chips, and a memory bank is defined as the grouping of DRAM chips containing the number of data bits required to support the full width of the data bus of the central processing unit (CPU), plus one parity bit for each byte (8 bits). For computers such as the IBM AT.RTM., this translates to an 18 bit bank width. For computers using the Intel.RTM. 386 CPU, a 36 bit bank width is required. In order to designate the amount of memory which has been inserted into the computer, computers generally have a plurality of switches which are manually set, or an electronic sensing circuit is used to detect how much memory has been inserted into the computer.
Existing computers require the memory chips (DRAMS) to be inserted in sequential sections because the computer system determines how much memory the system has installed in it by checking the memory up to the point where no chips are found at a particular location. Currently, DRAMS are available in different sizes and configurations, namely 256K, 1 Meg., and 4 Meg. sizes. For most existing digital computers and personal computers, it is necessary to insert different size DRAMS into the memory banks in a particular physical order or arrangement.
Each memory bank also can accommodate only one size of DRAMS. For a typical initial installation, this is not a problem, since the computer is initialized or set up with a specific default assignment by means of programmable switches or the like, to designate the type of and amount of memory in the computer. In addition, the physical arrangement of the DRAM chips, where chips of different memory size are used, initially is typically effected in the physical order or arrangement which the computer is designed to accommodate.
Because of the requirements for utilizing switches to indicate the size and location of the DRAMS in associated memory banks, prior art systems of the type described above are relatively costly and inflexible. A particular problem arises when additional DRAM chips are added to the computer after an initial installation, or whenever there is a failure or partial failure of DRAM chips in a memory bank already installed in the system. The physical removal and relocation of previously existing DRAM chips generally is required when new DRAM chips of different sizes from those previously installed are to be plugged into the DRAM sockets. Consequently, it is necessary to have an understanding of the physical requirements of the system in order to properly install a memory for operation within the system. A similar situation exists when there is a failure of a DRAM chip or a portion of a DRAM chip in a location other than the highest or last location of the memory. Such a failure has the effect of changing the amount of memory available and, frequently, renders operation of the system with the remaining DRAM chips impossible until there is an actual, physical relocation of the remaining DRAM chips in the system.
A system employing two programmable registers for controlling each bank of DRAM chips has been designed for overcoming the limitations of the prior art devices discussed above. In this system, two programmable registers are used to control each bank of DRAM chips. One register specifies the type of DRAM (that is, the size ) populating that memory bank. The second programmable register specifies the starting address at which the memory bank is accessed. Such a system permits arrangement of the physical DRAM banks in other than a pure sequential order; so that greater flexibility in the physical installation of the DRAM chips is permitted. This system, however, still has some disadvantages. For example, since a starting address must be programmed for each DRAM bank, the DRAM banks can be programmed in such a manner that the address ranges overlap. This can cause system errors. In addition, the control of this system is embedded in the memory controller; so that the logic involved is complex, and reduces the timing margin in critical paths of the system. It is necessary to provide logic to compare each address to the stored internal address in a programmable register. A decision then is made as to which control strobes must be generated in order to drive the proper DRAM bank. This logic comparison adds additional delay to the system operation, in addition to increasing the system complexity.
Accordingly, it is desirable to provide a programmable memory addressing system for a computer memory which overcomes the disadvantages of the prior art systems mentioned above, which prevents overlap of memory space, and which also generates sequential addressing to the DRAM chips in the memory with memory chips of different sizes being physically insertable into any of the memory banks.